An adaptive parallel genetic algorithm for VLSI-layout optimization

Abstract

The generation of a high quality layout during the design of a VLSI microchip is a very complex combinatorial optimization problem. Components of a circuit have to be placed, and signal nets have to be routed on an overall minimal area. In this paper a parallel Genetic Algorithm for the combined optimization of placement and routing is presented. The main focus is on the self-adaptation of the search process: Several islands execute a sequential GA with different strategies. At fixed intervals these strategies are ranked and each strategy is adjusted to the next better one by assimilating its characteristical parameters. © 1996, Springer-Verlag. All rights reserved.