Genetic design of VLSI-layouts
| Autor(en): | Schnecke, V. Vornberger, O. |
Stichwörter: | Computational complexity; Integrated circuit layout; Mathematical operators; Microprocessor chips; Optimization; Problem solving; VLSI circuits, Genetic design; Routing, Genetic algorithms | Erscheinungsdatum: | 1995 | Herausgeber: | IEE, Stevenage | Journal: | IEE Conference Publication | Ausgabe: | 414 | Startseite: | 430 | Seitenende: | 435 | Zusammenfassung: | A genetic algorithm for the physical design of VLSI-chips is presented. The algorithm simultaneously optimizes the placement of the cells with the total routing. During the placement the detailed routing is done, while the global routes are optimized by the genetic algorithm. This is just opposed to the usual serial approach, where the computation of the detailed routing is the last step in the layout-design. |
Beschreibung: | Conference of Proceedings of the 1st IEE/IEEE International Conference on Genetic Algorithms in Engineering Systems: Innovations and Applications GALESIA '95 ; Conference Date: 12 September 1995 Through 14 September 1995; Conference Code:43812 |
ISSN: | 05379989 | DOI: | 10.1049/cp:19951087 | Externe URL: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0029205039&doi=10.1049%2fcp%3a19951087&partnerID=40&md5=0629942594935017f4b086867441a117 |
Show full item record
