Translating timing requirements of Embedded Software systems modeled in Simulink to a timing analysis model

Abstract

In model-based Embedded Software Engineering (ESE), individual systems are modeled with chains of components that are translated to chains of tasks/runnables for a scheduling analysis. Early analysis of response time of such systems (e.g. end-to-end path delay) provides important feedback to understand how the function blocks/components in the system may actually behave. In this paper we report on work in progress pertaining to an overall workflow for model-driven specification, translation and validation of such timing constraints in ESE projects developed using Matlab/Simulink. The challenges addressed in this workflow and future directions are outlined. © 2016 IEEE.