SAccO: An implementation platform for scalable FPGA accelerators

DC ElementWertSprache
dc.contributor.authorWeinhardt, Markus
dc.contributor.authorLang, Bernhard
dc.contributor.authorThiesing, Frank M.
dc.contributor.authorKrieger, Alexander
dc.contributor.authorKinder, Thomas
dc.date.accessioned2022-04-19T14:04:01Z-
dc.date.available2022-04-19T14:04:01Z-
dc.date.issued2015
dc.identifier.issn0141-9331
dc.identifier.urihttps://osnascholar.ub.uni-osnabrueck.de/handle/unios/52500-
dc.publisherElsevier
dc.relation.ispartofMicroprocessors and Microsystems
dc.subjectComputer science
dc.subjectComputer hardware
dc.subjectScalability
dc.subjectEmbedded system
dc.subjectComputer architecture
dc.subjectField-programmable gate array
dc.subjectSoftware
dc.subjectHardware acceleration
dc.titleSAccO: An implementation platform for scalable FPGA accelerators
dc.typejournal article
dc.identifier.doihttps://doi.org/10.1016/j.micpro.2015.03.004
dc.description.volume39
dc.description.issue7
dc.description.startpage543
dc.description.endpage552
dc.identifier.externalhttps://openalex.org/W2088576620
local.import.sourcefileopenalex_uos_20220409.ris
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