A Survey of Domain-Specific Architectures for Reinforcement Learning
DC Element | Wert | Sprache |
---|---|---|
dc.contributor.author | Rothmann, Marc | |
dc.contributor.author | Porrmann, Mario | |
dc.date.accessioned | 2023-02-17T11:32:14Z | - |
dc.date.available | 2023-02-17T11:32:14Z | - |
dc.date.issued | 2022 | |
dc.identifier.issn | 2169-3536 | |
dc.identifier.uri | http://osnascholar.ub.uni-osnabrueck.de/handle/unios/65302 | - |
dc.description.abstract | Reinforcement learning algorithms have been very successful at solving sequential decision-making problems in many different problem domains. However, their training is often time-consuming, with training times ranging from multiple hours to weeks. The development of domain-specific architectures for reinforcement learning promises faster computation times, decreased experiment turn-around time, and improved energy efficiency. This paper presents a review of hardware architectures for the acceleration of reinforcement learning algorithms. FPGA-based implementations are the focus of this work, but GPU-based approaches are considered as well. Both tabular and deep reinforcement learning algorithms are included in this survey. The techniques employed in different implementations are highlighted and compared. Finally, possible areas for future work are suggested, based on the preceding discussion of existing architectures. | |
dc.description.sponsorship | European Union's Horizon 2020 Research and Innovation Program through the Very Efficient Deep Learning in IoT (VEDLIoT) Project [957197]; This work was supported by the European Union's Horizon 2020 Research and Innovation Program through the Very Efficient Deep Learning in IoT (VEDLIoT) Project under Grant 957197. | |
dc.language.iso | en | |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | |
dc.relation.ispartof | IEEE ACCESS | |
dc.subject | Computer architecture | |
dc.subject | Computer Science | |
dc.subject | Computer Science, Information Systems | |
dc.subject | deep learning | |
dc.subject | deep reinforcement learning | |
dc.subject | Domain-specific architectures | |
dc.subject | Engineering | |
dc.subject | Engineering, Electrical & Electronic | |
dc.subject | FPGA | |
dc.subject | Graphics processing units | |
dc.subject | IMPLEMENTATION | |
dc.subject | LEVEL | |
dc.subject | machine learning | |
dc.subject | Neural networks | |
dc.subject | Optimization | |
dc.subject | Q-learning | |
dc.subject | reconfigurable architectures | |
dc.subject | reinforcement learning | |
dc.subject | Telecommunications | |
dc.subject | Training | |
dc.title | A Survey of Domain-Specific Architectures for Reinforcement Learning | |
dc.type | journal article | |
dc.identifier.doi | 10.1109/ACCESS.2022.3146518 | |
dc.identifier.isi | ISI:000753402400001 | |
dc.description.volume | 10 | |
dc.description.startpage | 13753 | |
dc.description.endpage | 13767 | |
dc.contributor.orcid | 0000-0003-2886-8197 | |
dc.publisher.place | 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA | |
dcterms.isPartOf.abbreviation | IEEE Access | |
dcterms.oaStatus | gold | |
local.import.remains | affiliations : University Osnabruck | |
local.import.remains | web-of-science-index : Science Citation Index Expanded (SCI-EXPANDED) | |
crisitem.author.dept | FB 06 - Mathematik/Informatik | - |
crisitem.author.deptid | fb06 | - |
crisitem.author.orcid | 0000-0003-1005-5753 | - |
crisitem.author.parentorg | Universität Osnabrück | - |
crisitem.author.netid | PoMa309 | - |
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geprüft am 23.05.2024