FAQ: A Flexible Accelerator for Q-Learning with Configurable Environment
DC Element | Wert | Sprache |
---|---|---|
dc.contributor.author | Rothmann, M. | |
dc.contributor.author | Porrmann, M. | |
dc.contributor.editor | Pericas, M. | |
dc.contributor.editor | Pnevmatikatos, D.N. | |
dc.contributor.editor | Trancoso, P.P.M. | |
dc.contributor.editor | Sourdis, I. | |
dc.date.accessioned | 2023-02-17T12:15:14Z | - |
dc.date.available | 2023-02-17T12:15:14Z | - |
dc.date.issued | 2022 | |
dc.identifier.isbn | 9781665483087 | |
dc.identifier.issn | 1063-6862 | |
dc.identifier.uri | http://osnascholar.ub.uni-osnabrueck.de/handle/unios/65890 | - |
dc.description | Conference of 33rd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2022 ; Conference Date: 12 July 2022 Through 14 July 2022; Conference Code:183622 | |
dc.description.abstract | Reinforcement Learning is an area of machine learning that is concerned with optimizing the behavior of an agent in an environment by maximizing cumulative rewards. This can be done with classical reinforcement learning algorithms such as Q-Learning and SARSA. This paper presents FAQ, a flexible FPGA-based accelerator for the Q-Learning algorithm. The architecture of the accelerator can be configured in multiple ways, like adjusting the bit width of Q-values or changing the number of pipeline stages. The evaluation shows that FAQ achieves 249% higher throughput than state-of-the-art FPGA implementations while decreasing DSP and BRAM utilization. Additionally, a software-configurable environment was implemented, and the whole system was tested on an Ultra96-V2 development board utilizing the PYNQ framework. Compared to a CPU implementation, FAQ is more than 13 times faster, including communication overhead caused by transferring the environment onto the FPGA and reading the resulting Q-table. © 2022 IEEE. | |
dc.description.sponsorship | 957197; This publication incorporates results from the VEDLIoT project, which received funding from the European Union s Horizon 2020 research and innovation programme under grant agreement No 957197; Gaisler | |
dc.language.iso | en | |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | |
dc.relation.ispartof | Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors | |
dc.subject | Domain specific architectures | |
dc.subject | Domain-specific architectures | |
dc.subject | Field programmable gate arrays (FPGA) | |
dc.subject | High-throughput | |
dc.subject | Learning algorithms | |
dc.subject | Machine Learning | |
dc.subject | Machine-learning | |
dc.subject | NASA | |
dc.subject | Pipeline stages | |
dc.subject | Q-learning | |
dc.subject | Q-learning algorithms | |
dc.subject | Q-values | |
dc.subject | Reconfigurable architectures | |
dc.subject | Reconfigurable hardware | |
dc.subject | Reinforcement Learning | |
dc.subject | Reinforcement learning algorithms | |
dc.subject | Reinforcement learnings, Reinforcement learning | |
dc.subject | Software testing, Bit-Width | |
dc.title | FAQ: A Flexible Accelerator for Q-Learning with Configurable Environment | |
dc.type | conference paper | |
dc.identifier.doi | 10.1109/ASAP54787.2022.00026 | |
dc.identifier.scopus | 2-s2.0-85140964922 | |
dc.identifier.url | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85140964922&doi=10.1109%2fASAP54787.2022.00026&partnerID=40&md5=d0d93433951d00e19634419bf07a4e81 | |
dc.description.volume | 2022-July | |
dc.description.startpage | 106 | |
dc.description.endpage | 114 | |
dcterms.isPartOf.abbreviation | Proc Int Conf Appl Spec Syst Arcitec Process Proc | |
crisitem.author.dept | FB 06 - Mathematik/Informatik | - |
crisitem.author.deptid | fb06 | - |
crisitem.author.orcid | 0000-0003-1005-5753 | - |
crisitem.author.parentorg | Universität Osnabrück | - |
crisitem.author.netid | PoMa309 | - |
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geprüft am 23.05.2024