ReDroSe - Reconfigurable Drone Setup for Resource-Efficient SLAM

DC ElementWertSprache
dc.contributor.authorRahn, Sebastian
dc.contributor.authorGehricke, Philipp
dc.contributor.authorPetermöller, Can-Leon
dc.contributor.authorNeumann, Eric
dc.contributor.authorSchlinge, Philipp
dc.contributor.authorRabius, Leon
dc.contributor.authorTermühlen, Henning
dc.contributor.authorSieh, Christopher
dc.contributor.authorTassemeier, Marco
dc.contributor.authorWiemann, Thomas
dc.contributor.authorPorrmann, Mario
dc.date.accessioned2023-07-12T06:59:21Z-
dc.date.available2023-07-12T06:59:21Z-
dc.date.issued2023
dc.identifier.isbn9798400700453
dc.identifier.urihttp://osnascholar.ub.uni-osnabrueck.de/handle/unios/72048-
dc.descriptionCited by: 0; Conference name: Workshop on System Engineering for Constrained Embedded Systems - Drone Systems Engineering and Rapid Simulation and Performance Evaluation: Methods and Tools, DroneSE and RAPIDO 2023 - Presented at HiPEAC 2023 Conference; Conference date: 16 January 2023 through 18 January 2023; Conference code: 187920
dc.description.abstractIn this paper we present ReDroSe, a heterogeneous compute system based on embedded CPUs, FPGAs and GPUs, which is integrated into an existing UAV platform to allow real time SLAM based on a Truncated Signed Distance Field (TSDF) directly on the drone. The system is fully integrated into the existing infrastructure to allow ground control to manage and monitor the data acquisition process. ReDroSe is evaluated in terms of power consumption and computing capabilities. The results show that the proposed architecture allows computations on the UAV that were previously only possible in post-processing while keeping the power consumption low enough to match the available flight time of the UAV. © 2023 ACM.
dc.language.isoen
dc.publisherAssociation for Computing Machinery
dc.relation.ispartofACM International Conference Proceeding Series
dc.subjectComputing power
dc.subjectData acquisition
dc.subjectDigital storage
dc.subjectDrone
dc.subjectDrones
dc.subjectElectric power utilization
dc.subjectEmbedded CPU
dc.subjectField Programmable Gate Array
dc.subjectField programmable gate arrays (FPGA)
dc.subjectField programmables
dc.subjectGPU
dc.subjectGraphics processing unit
dc.subjectGreen computing
dc.subjectHardware Acceleration
dc.subjectHeterogeneous Computing
dc.subjectInformation management
dc.subjectProgram processors
dc.subjectProgrammable gate array
dc.subjectReconfigurable
dc.subjectResource-efficient
dc.subjectRock mechanics
dc.subjectROS
dc.subjectUAV
dc.subjectUAV platform
dc.titleReDroSe - Reconfigurable Drone Setup for Resource-Efficient SLAM
dc.typeconference paper
dc.identifier.doi10.1145/3579170.3579266
dc.identifier.scopus2-s2.0-85156242062
dc.identifier.urlhttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85156242062&doi=10.1145%2f3579170.3579266&partnerID=40&md5=b301f7ca75680bed06cc1933bc28fa28
dc.description.startpage20 – 30
dcterms.isPartOf.abbreviationACM Int. Conf. Proc. Ser.
local.import.remainsaffiliations : Osnabrück University, Osnabrück, Germany
local.import.remainspublication_stage : Final
crisitem.author.deptFB 06 - Mathematik/Informatik-
crisitem.author.deptFB 06 - Mathematik/Informatik-
crisitem.author.deptidfb06-
crisitem.author.deptidfb06-
crisitem.author.orcid0000-0003-0710-872X-
crisitem.author.orcid0000-0003-1005-5753-
crisitem.author.parentorgUniversität Osnabrück-
crisitem.author.parentorgUniversität Osnabrück-
crisitem.author.netidWiTh428-
crisitem.author.netidPoMa309-
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