CyPhOS – A component-based cache-aware multi-core operating system
| Autor(en): | Borghorst, H. Spinczyk, O. |
Herausgeber: | Uhrig, S. Hochberger, C. Schoeberl, M. Pionteck, T. Brehm, J. |
Stichwörter: | Component-based design; Load testing; Memory architecture, Component based design; Multi core; Multi-core; Operating system; Real time; Real-time; Timing predictability; Timing predictability, Cache memory | Erscheinungsdatum: | 2019 | Herausgeber: | Springer Verlag | Journal: | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | Volumen: | 11479 LNCS | Startseite: | 171 | Seitenende: | 182 | Zusammenfassung: | Off-the-shelf multi-core processors provide a cost-efficient alternative to expensive special purpose processors at the cost of complex time predictability due to shared resources like buses, caches and the memory itself. This paper presents an operating system concept that takes control over the shared cache to minimize contention, by creating a component-based operating system, that is structured in small data chunks to allow better control over data and code movement in and out of the cache. An evaluation of the operating system shows that the system is able to reduce the difference between the ACET and observed WCET of a synthetic memory load test by 93% for ARM and 98% for Intel systems. Some noteworthy improvements were also achieved for the TACLe benchmarks. © Springer Nature Switzerland AG 2019. |
Beschreibung: | Conference of 32nd International Conference on Architecture of Computing Systems, ARCS 2019 ; Conference Date: 20 May 2019 Through 23 May 2019; Conference Code:226179 |
ISBN: | 9783030186555 | ISSN: | 03029743 | DOI: | 10.1007/978-3-030-18656-2_13 | Externe URL: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85065893978&doi=10.1007%2f978-3-030-18656-2_13&partnerID=40&md5=3dc1a14d4aee731a3ec2b017db5ef553 |
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